| 摘要 |
PURPOSE: A de-capsulation preventing semiconductor IC(Integrated Circuit) is provided to detect weather a secure membrane, namely an oxidation membrane, formed at a surface on an IC chip, is erased or de-capsulated. CONSTITUTION: The circuit comprises the first and the second voltage distributor(120, 140), a comparator(160), a PMOS transistor(MP4), an NMOS transistor(MN3), and an inverter(INV). The first voltage distributor(120), including metal line capacitors, distributes a power source voltage(VDD), and outputs the first voltage to a node(ND1). The metal line capacitors of the first voltage distributor(120) are serially connected between the power source voltage(VDD) and a ground voltage(VSS). The second voltage distributor(140), including metal line capacitors, distributes a power source voltage(VDD), and outputs the second voltage to a node(ND2). The metal line capacitors of the second voltage distributor(140) are serially connected between the power source voltage(VDD) and the ground voltage(VSS). The comparator(160), including three PMOS transistors and two NMOS transistors, compares the first voltage with the second voltage, and outputs a comparison signal. The PMOS transistors and the NMOS transistors are serially connected between the power source voltage(VDD) and the ground voltage(VSS), and controlled by a bias voltage and an output of the comparator(160). The inverter(INV) is connected to a common access node of the transistors(MP4, MN3), and outputs a de-capsulation detection signal according to a voltage level of the common access node.
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