SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor test method in which a test time is short. SOLUTION: In a final test of a multi-layer memory IC1, a test of a SRAM chip 2 and a test of a flash memory chip 3 are performed in parallel. For example, a test of the flash memory chip 3 is performed during a data holding period of a hold-test of the SRAM chip 2. Therefore, a test time can be shortened compared with the conventional one in which a test of the SRAM chip 2 is performed after finish of a test of the flash memory chip 3.