| 摘要 |
PURPOSE: A sense amplifier enable circuit is provided to prevent a malfunction of a sense amplifier by removing a short pulse from an inside of a chip. CONSTITUTION: The first inverter(IN1) is used for inverting an output signal of a pulse removal portion. The first signal delay portion(21) is used for delaying an output signal of the first inverter(IN1). The first NAND gate(NAND1) is used for performing a logical AND operation for an output signal of the first inverter(IN1) and an output signal of the first signal delay portion(21). The second signal delay portion(22) is used for delaying an output signal of the first NAND gate(NAND1). The second NAND gate(NAND2) is used for performing the logical AND operation for the output signal of the first inverter(IN1) and an output signal of the second signal delay portion(22). The first NOR gate(NOR1) is used for performing a logical OR operation for an output signal of the second NAND gate(NAND2) and a ground voltage signal. The third and the fourth signal delay portions(23,24) are used for delaying an output signal of the first NOR gate(NOR1). The third NAND gate(NAND3) is used for performing a logical AND operation for output signals of the third and the fourth signal delay portions(23,24). The second inverter(IN2) is used for inverting an output signal of the third NAND gate(NAND3). The fourth NAND gate(NAND4) is used for performing the logical AND operation for an output signal of the second inverter(IN2) and a supply voltage signal. The third inverter(IN3) is used for inverting an output signal of the fourth NAND gate(NAND4).
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