发明名称 FREQUENCY CONVERTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce errors in the frequency set value of a horizontal synchronization circuit due to input frequency by conducting signal operations, in which the horizontal frequency is made approximately constant in matching with the characteristics of a CRT monitor, and the vertical frequency is set to the frequency that is determined by the number of input lines and the vertical fly-back time. SOLUTION: The circuit is provided with a frame memory 31, which stores input video signals, PLLs 36 to 38 which generate read clocks of the memory 31 based on a reference clock, a timing pulse generating circuit 34 which controls the memory 31, a signal discriminating circuit 35 which discriminates the synchronization frequency of the input video signals, and a timing control circuit 39 which controls the circuit 34 and a frequency divider 38, based on the discrimination result of the synchronization frequency, writes the input video signals into the memory 31, makes the horizontal synchronization frequency, the horizontal fly-back interval and the vertical fly-back interval approximately constant, regardless of the horizontal synchronization frequency of the input video signals, reads the video signals from the memory 31 and outputs them and outputs the horizontal synchronization frequency data of output video signals.
申请公布号 JP2002304166(A) 申请公布日期 2002.10.18
申请号 JP20010107650 申请日期 2001.04.05
申请人 SONY CORP 发明人 YAMAZAKI NOBUO
分类号 H04N5/04;G09G5/00;G09G5/18;(IPC1-7):G09G5/00 主分类号 H04N5/04
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