| 摘要 |
PURPOSE: A method for fabricating a capacitor of a dynamic random access memory(DRAM) is provided to improve step coverage between a DRAM area and a logic circuit area, by forming two poly conductive layers of wordlines and bitlines and two metal layers of lower and upper electrodes in the DRAM area and by twice performing a planarization process. CONSTITUTION: After a memory cell region and a logic circuit region are defined in a semiconductor substrate(100), the first and second insulation layers(101,102) are sequentially formed on the resultant structure. A storage contact hole is formed in the memory cell region while an intermetallic contact hole is formed in the logic circuit region. The first metal layer(103a,103b) is formed in the storage contact hole and the intermetallic contact hole. A plurality of the second metal layers(104a,104b) are connected to the first metal layer. The third insulation layer(105) having a via hole is formed on the second metal layer and the second metal layer in the logic circuit region so that the second metal layer in the memory cell region is exposed by a predetermined portion. The third metal layer pattern(108b) is connected to the second metal layer in the logic circuit region while the third metal layer spacer(108a) is formed on the second metal layer and the sidewall of the third insulation layer in the memory cell region. The third insulation layer in the memory cell region is eliminated. A dielectric layer(109) is formed in the memory cell region. The fourth metal layer(110) which is selectively patterned is formed on the entire surface of the substrate.
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