发明名称 INTERCONNECTION METHOD AND STRUCTURE THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To provide an electronic package, in which an opened window is arranged above a device active region and a wiring having a large number of pins is installed. SOLUTION: An interconnection structure includes a dielectric layer (10); a first metallization pattern (12) on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter (22) defined at least one etch stop opening (24); a cured adhesive (38) on a portion of the dielectric layer, the adhesive not being present in an area aligned with at least one etch stop; and at least one electrical device (16) being attached to the dielectric layer by the adhesive, such that the active area (20) of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optical additional portion (150) of cured adhesive, the additional portion of the cured adhesive which is attached adhesively to the dielectric layer and not attached adhesively to at least one electrical device.</p>
申请公布号 JP2002305199(A) 申请公布日期 2002.10.18
申请号 JP20010382426 申请日期 2001.12.17
申请人 GENERAL ELECTRIC CO <GE> 发明人 BURDICK WILLIAM EDWARD JR;ROSE JAMES WILSON;DUROCHER KEVIN MATTHEW;FILLION RAYMOND A
分类号 H01L23/52;H01H;H01L21/3205;H01L21/48;H01L21/60;H01L23/12;H01L23/34;H01L23/50;H01L23/538;H01P1/04;H05K3/06;H05K3/38;(IPC1-7):H01L21/320 主分类号 H01L23/52
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