SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH WORD LINE DEFECT CHECK CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a defect check circuit. SOLUTION: In a non-volatile semiconductor memory device provided with a memory cell array comprising a plurality of cell array blocks having a plurality of cell strings consisting of floating gate memory cell transistors in which control gates are connected respectively to a plurality of word lines and a drain and a source channel are connected in series between string select transistors and ground select transistors, the device is provided with a word line short circuit check circuit in which voltage of different levels are applied to an adjacent word line out of word lines during a charging time, after elapse of the charging time, a voltage level of a word line to which voltage of the same level out of word lines is applied is checked, and which generates a short circuit sensing signal indicating existence of occurrence of short circuit between adjacent word lines being at least one or more.