Isolated high voltage MOS transistor

摘要

The present invention relates to an NMOS transistor structure which comprises a p-well region in a semiconductor substrate, an n-type source region in the p-well region, and an n-type drain region in the p-well region. The source and drain regions are laterally spaced apart from one another and define a p-type channel region therebetween in the p-well region. The NMOS transistor further comprises a gate having a gate electrode and a gate oxide overlying the channel region of the p-well region. A PDUF region underlies the p-well region and exhibits a resistivity which is less than the p-well region, wherein the PDUF region lowers a resistance associated with the p-well region at high drain voltages. The lowered resistance decreases a gain associated with a parasitic bipolar transistor and increases an injection induced breakdown voltage characteristic of the NMOS transistor structure.