Management system for real-time interrupt requests e.g. for computing and processing resources units, includes priority decoder for each of three planes

摘要

A system for managing interrupts has a priority decoder (10,Bn,Cn) with several interrupt inputs (int-i) to which are connected several interrupt sources (B1,B2).The priority decoder (10,Bn,Cn) has a circuit for conversion of a signal present at the interrupt input (int-i) into a vectorally coded address of the corresponding interrupt source, which is outputted at the address (addrh) of the priority decoder (10,Bn,Cn) and supplied to a CPU. An Independent claim is given for a method for managing interrupt requests of system devices.