发明名称 Error correction code circuits
摘要 This invention discloses a method for changing a configuring ot an error correction code (ECC) logic circuit for performing an error-check of a changed data-width. The method includes the steps of: A) sequentially interconnecting a set of N1 identical error-check blocks where N1 is a first positive integer. And, the method further includes a step B) of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits comprising N2 of the identical error-check blocks where N2 is a second positive number. In a preferred embodiment, the step of sequentially interconnecting a set of N1 identical error-check blocks is a step of interconnecting the N1 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks. And, the step of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits is a step of interconnecting the N2 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks.
申请公布号 US2002152442(A1) 申请公布日期 2002.10.17
申请号 US20010038268 申请日期 2001.10.22
申请人 SHAU JENG-JYE 发明人 SHAU JENG-JYE
分类号 G11C7/10;G11C7/18;G11C8/12;G11C11/406;G11C11/4091;G11C11/4096;G11C11/4097;H01L27/108;(IPC1-7):H03M13/00 主分类号 G11C7/10
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