| 摘要 |
The present invention provides an error correction circuit for receiving and decoding a trellis-encoded signal of a series of data Zq, Zq-1, . . . ,Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits Xt, Xt-1, . . . ,X1 of an input p-bit series of data Xp, Xp-1, . . . , X1 (where p>=2, q>=p, and p>t>=1), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit includes: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.
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