| 摘要 |
<p>A DRAM capable of reducing the access loss time during refresh, performing refresh of another bank simultaneously with an ordinary access, and being handled in the same way as an SRAM. The DRAM comprises execution instruction means for instructing execution of refresh, bank specification means for specifying a bank number of a memory cell to be refreshed, address specification means for specifying a row address of the memory cell to be refreshed within a specified bank, and execution means for refreshing the memory cell of the row address specified by the address specification means in the bank specified by the bank specification means when execution of refresh is instructed from the execution instruction means.</p> |
