发明名称 |
Fast cycle RAM and data readout method therefor |
摘要 |
A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.
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申请公布号 |
US2002149993(A1) |
申请公布日期 |
2002.10.17 |
申请号 |
US20020163797 |
申请日期 |
2002.06.04 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
OHSHIMA SHIGEO;WATANABE NOBUO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/401;G11C11/406;G11C11/4076;G11C11/409;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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