发明名称 Power down protocol for integrated circuits
摘要 A system-on-chip (SOC) includes a power down circuit. Within the SOC are several circuit blocks, each of them operating responsive to a local clock signal. A system clock is coupled to the circuit blocks for providing a system clock signal that functions as the local clock signal for selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock signal from functioning as the local clock signal in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shutdown is received from the power control manager and after the circuit block has, in fact, shutdown.
申请公布号 US2002152407(A1) 申请公布日期 2002.10.17
申请号 US20010010738 申请日期 2001.11.05
申请人 STMICROELECTRONICS S.R.I. 发明人 ALIA MICHELE;CARRANO MICHELE;PISTRITTO CARMELLO
分类号 G06F1/32;(IPC1-7):G06F1/26 主分类号 G06F1/32
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