发明名称 Multiplizier- und Integrierglied
摘要 The pulse width modulator has an integrator and write/read input gates and is connected on the output side to the control input of a gate whose working input receives signals from another multiplier. The write gate (10) control input is connected to the clock pulse generator and to a differentiator (14). The differentiator and the output of a zero indicator (12) on the output side of the integrator (11) are connected to separate inputs of a flip-flop, (13) whose output is connected to the control input of the read gate (15). The flip-flop output is connected to the clock pulse input of a further pulse width modulator and only then to the control input of a gate on the output side.
申请公布号 DE1800072(A1) 申请公布日期 1970.06.18
申请号 DE19681800072 申请日期 1968.10.01
申请人 NAUCNO-ISSLEDOVATELSKIJ I KONSTRUKTORSKO-TECHNOLOGICESKIJ INSTITUT GORODSKOGO CHOZJAJSTVA 发明人 I. ZABARNIJ,ANATOLIJ
分类号 G01K17/16;G01R21/127;G06G7/161;G06J1/00;H03K7/08 主分类号 G01K17/16
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