| 摘要 |
<p>The operation of a microcomputer in a state in which the microcomputer cannot be monitored properly is prevented. A microcomputer is started and an output signal Q of a determination circuit 36 is reset by a reset signal RS output from a watchdog circuit 34. Thereafter, when a clock signal ck is input from the started microcomputer, the determination circuit outputs a clock signal CK to the watchdog circuit and sets the output signal. However, when the standby signal st is detected at the time of starting the microcomputer, the output of the clock signal CK and the set of the output signal Q are stopped. In this way, the standby signal ST is not output from the AND circuit 38 to the watchdog circuit, the output of the reset signal from the watchdog circuit is repeated, and the microcomputer does not operate. <IMAGE></p> |
