发明名称 Reading circuit and method for a multilevel non volatile memory
摘要 <p>The reading circuit comprises an asynchronous serial dichromatic reader (12,14,16). The reader includes a comparator (12). An output of the comparator supplies one of the bits stored in the multilevel memory cell (18). A selector (16) has a selection input connected to the output of the comparator and two signal inputs. The selector has an output selectively connectable to one of the two signal inputs depending on the logic level on the selection input. The circuit further includes a second comparator (14). An independent claim is also included for the following: (a) a reading method for a multilevel memory cell.</p>
申请公布号 EP1249841(A1) 申请公布日期 2002.10.16
申请号 EP20010830248 申请日期 2001.04.10
申请人 STMICROELECTRONICS S.R.L. 发明人 PAGLIATO, MAURO;ROLANDI, PAOLO;MONTANARO, MASSIMO
分类号 G11C11/56;(IPC1-7):G11C11/56 主分类号 G11C11/56
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