| 摘要 |
A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD. The I/O is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the I/O and selectively coupling the local wordlines to the VDD node.
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