| 摘要 |
PROBLEM TO BE SOLVED: To reduce a wiring resistance of an earthed wiring and a power source without enlarging a chip area in a semiconductor memory device of a process using only two metallic wiring layers. SOLUTION: In an earthed wiring 108 in a memory cell plate region 101 and in a sense amplifier region 102, the wiring is wired so as to pass among column selecting wires YSW (first AL wiring) in the memory cell plate region 101 (an earthed wiring part A) from the earthed wiring 108 wired to an X- decoder 105 with a second AL wiring through both the end parts of the sense amplifier region 102 (an earthed wiring part A). |
