发明名称 |
Technique for intralevel capacitive isolation of interconnect paths |
摘要 |
A technique is described for providing cavities between the conducting paths of an integrated semiconductor circuit. These cavities can have air or a gas trapped therein to decrease the dielectric constant between two conducting paths. After forming the conducting paths, an etchable fill material formed between and over the conducting paths. An oxide cap is formed over the fill material. Conducting plugs, extending through the fill material and the oxide cap, and electrically coupled to the conducting paths are formed. A photo-resist layer applied over the conducting plugs and the oxide cap. The photo-resist layer is structured to permit access to the oxide cap between the conducting plugs. A "pin-hole" is fabricated through the oxide cap and the fill material exposed by the "pin-hole" is etched away. The "pin-hole" is plugged with additional oxide cap material and a surface is then formed on the oxide cap exposing the conducting plugs. This structure is then ready for additional processing.
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申请公布号 |
US6465339(B2) |
申请公布日期 |
2002.10.15 |
申请号 |
US19980216240 |
申请日期 |
1998.12.18 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BRANKNER KEITH;BRENNAN KENNETH D.;SHAW YVETTE |
分类号 |
H01L21/316;H01L21/768;H01L23/522;(IPC1-7):H01L21/44;H01L21/476 |
主分类号 |
H01L21/316 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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