发明名称 Method of improving the planarization of wiring by CMP
摘要 A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of "Erosion' to be prevented, as well as it is capable of being prevented occurrence of "micro-scratch' on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.
申请公布号 US6465354(B1) 申请公布日期 2002.10.15
申请号 US19990435612 申请日期 1999.11.08
申请人 NEC CORPORATION 发明人 SUGAI KAZUMI;ITO NOBUKAZU;TACHIBANA HIROAKI
分类号 H01L21/3205;C25D5/48;C25D7/12;H01L21/288;H01L21/768;(IPC1-7):H01L21/44;H01L21/302;H01L21/476 主分类号 H01L21/3205
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