发明名称 Level converter circuit
摘要 A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.
申请公布号 US6466054(B2) 申请公布日期 2002.10.15
申请号 US20010811699 申请日期 2001.03.20
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KAMEYAMA ATSUSHI;FUSE TSUNEAKI;OHUCHI KAZUNORI;YOSHIDA MASAKO
分类号 G11C7/10;H03K19/0185;(IPC1-7):H03K19/017 主分类号 G11C7/10
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