发明名称 DRAM with intermediate storage cache and separate read and write I/O
摘要 A memory device which includes intermediate storage, or cache, and unidirectional data paths coupling the intermediate storage to external input/output. The invention improves the response of the memory device by eliminating dual latencies associated with the transition from a write request to a read request. The method of use of the invention and systems incorporating the invention are further described.
申请公布号 US6466507(B2) 申请公布日期 2002.10.15
申请号 US20010756622 申请日期 2001.01.08
申请人 MICRON TECHNOLOGY, INC. 发明人 RYAN KEVIN J.
分类号 G06F12/08;G11C11/4093;(IPC1-7):G11C8/00 主分类号 G06F12/08
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