发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To reduce occurrence of wiring penalty of a semiconductor memory. SOLUTION: An address input circuit 30 receives an input of an address signal. A drive circuit 31 drives a memory array in accordance with an address signal. A signal line 32 connects the address input circuit 30 to the drive circuit 31. A redundancy circuit 33 is arranged near the drive circuit 31, and replaces a defective line existing in the memory array by the other line including a redundancy line. A supply circuit 35 supplies information stored in a defective line information storing circuit 34 to the redundancy circuit 33 through the signal line 32. By using such constitution, an address signal and a defective line information can be transmitted by the common signal line 32, the number of wirings can be reduced and occurrence of wiring penalty can be reduced.
申请公布号 JP2002298593(A) 申请公布日期 2002.10.11
申请号 JP20010096344 申请日期 2001.03.29
申请人 FUJITSU LTD 发明人 YAGISHITA YOSHIMASA;UCHIDA TOSHIYA
分类号 G11C29/04;G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/04
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