| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock recovery circuit that suppresses timing jitter in a recovered clock. SOLUTION: A driver 5 and a receiver 10 respectively supply serial data having a regular bit pattern such as a clock, which includes 1's and 2's alternately with each other during an adjustment period and supply a data signal (IDATA) on the basis of serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller(DFC) 20 adjusts a data transition characteristic of the driver or the receiver so that the duty factor(DF) of the data signal supplied from the receiver 10 is equal to 50% in the adjustment period and stores the adjusted data. A clock recovery unit(CRU) 15 recovers a clock(CK) synchronized with the data signal, which is supplied from the receiver 10 in the transmission period and is based on the adjusted transition characteristic, from the data signal. |
