| 摘要 |
PURPOSE: To provide a level shift circuit that can be operated at a higher speed. CONSTITUTION: N-channel MOS transistors (TRs) N3 and NS3 are connected in series between a P-channel MOS TR P1 and an N-channel MOS TR N1S configuring a 1st inverter connected between a reference level VSS and a power supply level VDD2 (VDD1<VDD2) and similarly N-channel MOS TRs N4 and N4S are connected in series between a P-channel MOS TR P2 and an N-channel MOS TR N2S configuring a 2nd inverter. The gate insulation film of the P- channel MOS TRs P1, P2 and of the N-channel MOS TRs N3, N4 is thicker than that of the N-channel MOS TRs N1S-N4S. The gate of the N-channel MOS TRs N3, N4 is connected to the power supply level VDD2, the gate of the N-channel MOS TRs N3S, N4S is connected to the VDD1 and the TRs above are all normally conductive.
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