| 摘要 |
PROBLEM TO BE SOLVED: To provide a flip-flop circuit that can reduce the setup time and prevent the penetration due to clock skew without the need for a complicated and confusing design. SOLUTION: The flip-flop circuit is provided with a NAND gate 41 that receives 1st-3rd input signals and NANDs the 2nd input signal and the 1st input signal of a negative logic with the highest priority, a NAND gate 42 that NANDs the 1st and 3rd input signals, a multiplexer 43 that selects either of outputs of the NAND gates 41, 42, and a latch circuit 30 that latches any signal including the signal selected by the multiplexer 43. The flip-flop circuit is characterized in that asserting the 1st input signal to make the arithmetic results of the NAND gates 41, 42 equal to each other can select the operation conducted by the 1st input signal with the highest priority.
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