| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory with which tests of regular cells and spare cells can be performed in the same cycle and to reduce the cost required for the test. SOLUTION: This device is provided with a plurality of regular cell array and a spare cell array, a plurality of word line selection driving circuit selecting and driving word lines in the regular cell array and the spare cell array, the first decoding circuit which generates a selection signal of a word line based on the first address signal generated from an external address signal and supplies it to a plurality of word line selection and driving circuit, and the second decoding circuit which performs control for outputting the selection signal from one of a plurality of word line selection and driving circuit based on the second address signal generated from an external address signal. The word line selection and driving circuit outputs the selection signal to either a word line in the regular cell array or a word line in the corresponding spare cell array in accordance with the third address signal.
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