| 摘要 |
An integrated clock generator, particularly for driving a semiconductor memory with a test signal, in which a delay locked loop is provided which, in a first mode of operation, synchronizes an input signal with a reference signal and, in a second, freewheeling mode of operation, uses a connected adder to form a precisely settable delay between the test signal and the reference signal. To change over between the first mode of operation and the second mode of operation, a selection circuit is provided. The delay locked loop is connected to the I/O interface of the integrated circuit, so that the BIST data produced are advantageously available directly at the input of the semiconductor memory. The principle described affords a simple way of providing test signals which have a highly precise delay with respect to a reference signal, as is necessary for DRAMs with a great storage density, for example.
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