| 摘要 |
<p>The architecture of a nonvolatile memory array can be realized by a production process compatible with the MOS logic production process unlike conventional architectures of a nonvolatile memory array. If the resistance of the bit line is further lowered, the writing and/or reading speed can be further increased. If the self-alignment contact technique and the borderless contact technique are used, high density hardware of a density approximate to 4F2 can be realized. The contact region is formed across a memory array including four cells connected to one bit line by the same processing step as that of an opposite-conductivity type region for economy. Memory cells are two-dimensionally arranged in two first and second directions along with the contact region, a conductive bit line extending in the first direction, a conductive word line extending in the second direction, and a conductive control line.</p> |
