MEMORY ADDRESS AND DECODE CIRCUITS WITH ULTRA THIN BODY TRANSISTORS

摘要

The decoder (200) includes a number of vertical pillars extending outwardly from a semiconductor substrate (202) at intersections of output lines and address lines. Each pillar (201) includes a single crystalline first contact layer (204) and a second contact layer (206) separated by an oxide layer (208). The decoder further includes a number of single crystalline ultra thin vertical transistor that are selectively disposed adjacent the number of vertical pillars. Each single crystalline vertical transistor (210) includes an ultra thin single crystalline vertical first source/drain region (214) coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region (216) coupled to the second contact layer, and an ultra thin single crystalline vertical body region (212) which opposes the oxide layer and couples the first and the second source/drain regions.