发明名称 DATABASE FOR ELECTRONIC DESIGN AUTOMATION APPLICATIONS
摘要 A database for storing chip design information comprises a plurality of parallel arrays for storing a particular class of information. The union of related entries commencing at a given array index across the one or more parallel arrays of a particular class forms a structure for a given instance within a class. Between classes, individual records in an array may cross-reference, through an array index, records in other arrays. The inherent sequential nature of records stored in the array may be used as linking information, thus avoiding the requirement of storing linking pointers in memory. Rather than storing all of the coordinate or spatial information for a given shape, only the offset information from the preceding shape may be stored, with the assumption that the second shape starts at the ending point of the first shape. Certain default values or characteristics for information within the array records can be assumed unless overridden by an indicator in the array record. Allocation of storage space for data entries may be adaptively managed based on the size of the data to be stored, with allocation size being determined by the largest value of the stored entries, or a header code for the data entry indicating the number of bytes. The data header of each class may include a pointer indicating the position in memory of a main data header, which in turn contains pointers to the positions in memory of the other classes, allowing instances in a class to refer to related instances in the other classes through an integer index number without requiring the use of other pointers.
申请公布号 WO0129715(A3) 申请公布日期 2002.10.10
申请号 WO2000US28162 申请日期 2000.10.11
申请人 CADENCE DESIGN SYSTEMS, INC.;DOIG, ROBERT, C.;SCHEFFER, LOUIS, K. 发明人 DOIG, ROBERT, C.;SCHEFFER, LOUIS, K.
分类号 G06F12/00;G06F17/30;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F12/00
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