ON-CHIP CIRCUITS FOR HIGH SPEED MEMORY TESTING WITH A SLOW MEMORY TESTER

摘要

A memory system (26) on a semiconductor body (10) is tested by testing components (12, 14, 16) formed on the semiconductor body. A programmable clock signal generator (12) receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter (14) receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory (16) store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals (21a-21n) to access a separate predetermined look-up memory section (30-37), and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section.