发明名称 |
Multi-processor system apparatus |
摘要 |
A multi-processor system apparatus allows a compiler to perform a static scheduling action easily and can conduct the transfer of data packets without collision in response to a common pattern of simultaneous access demands. Processor elements are interconnected by a multi-stage interconnection network having multiple stages. As each of switching elements in the multi-stage interconnection network is preliminarily subjected to the static scheduling action of a compiler. The multi-stage interconnection network is emulated without producing collision of data. When the transfer of packets is carried out in one clos network arrangement of the multi-stage interconnection network, the scheduling of switching elements SE0 to SE3 in the exchanger at Level 1 is determined so that a packet lost in the arbitration is transferred through the free port of any applicable one of the switching elements.
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申请公布号 |
US2002147851(A1) |
申请公布日期 |
2002.10.10 |
申请号 |
US20020085132 |
申请日期 |
2002.03.01 |
申请人 |
MORIMURA TOMOHIRO;AMANO HIDEHARU |
发明人 |
MORIMURA TOMOHIRO;AMANO HIDEHARU |
分类号 |
G06F13/36;G06F15/173;(IPC1-7):G06F15/16 |
主分类号 |
G06F13/36 |
代理机构 |
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