| 摘要 |
A PLL device includes a programmable frequency-division device 111 that divides the frequency of the output of a voltage-controlled oscillator 112, a reference signal generating means 105 that generates a first reference signal and a second reference signal having different phases, a first comparator 106 that compares the phases of the first reference signal and the output of the programmable frequency-division device 111, a second comparator 110 that compares the phases of the second reference signal and the output of the programmable frequency-division device 111, a detector 118 that detects the locked state, and a control unit 117. With this structure, when the state is not locked, phase comparisons are performed by a plurality of comparators at different timings, so the locking time is shortened because more than one phase comparison is performed in one period of the reference signal. In the locked state, the phase comparisons are performed by one comparator, mitigating the increase in power consumption due to having multiple loops.
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