发明名称 |
Image processing apparatus |
摘要 |
An image processing circuit is provided in which a clock signal is divided according to bits of data input thereto and supply or interruption of the divided clock signals is controlled according to the value of the input data. Therefore, it becomes possible to interrupt the clock signal which is to be supplied for a bit among the bits of the input data which is not used for a long period of time and reduce the power consumption of the circuit.
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申请公布号 |
US2002145764(A1) |
申请公布日期 |
2002.10.10 |
申请号 |
US20010725686 |
申请日期 |
2001.04.05 |
申请人 |
TOSHIBA TEC KABUSHIKI KAISHA. |
发明人 |
SUZUKI MINORU |
分类号 |
H04N1/40;(IPC1-7):B41B1/00;G06F15/00 |
主分类号 |
H04N1/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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