发明名称 Reference frequency and facet to facet error correction circuit
摘要 A reference frequency and facet to facet correction circuit utilizes a phase locked loop which includes a digital phase detector to measure the time difference between the end of scan and the end of count of each facet and store them in a lookup table. The phase locked loop continuously generates an average time value form the time differences of all the facets of the polygon. The phase locked loop also adds the errors of each facet to the average time value and uses the result to correct the frequency of a pixel clock generator for both the reference frequency and facet to facet errors.
申请公布号 EP1119185(A3) 申请公布日期 2002.10.09
申请号 EP20000310864 申请日期 2000.12.07
申请人 XEROX CORPORATION 发明人 NEARY, MICHAEL B.
分类号 B41J2/44;G02B26/12;H04N1/113 主分类号 B41J2/44
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