发明名称 Circuit and method for merging refresh and access operations for a memory device
摘要 A memory controller to generate refresh requests for by storing the status of memory rows and an arithmetic logic unit to store a second status of all the memory rows of all the memory devices in the system memory configuration. A second logic unit stores the open status of the plurality of memory banks. The third logic generates a refresh request based on the open status and the second status in response to a refresh frequency.
申请公布号 US6463001(B1) 申请公布日期 2002.10.08
申请号 US20000663042 申请日期 2000.09.15
申请人 INTEL CORPORATION 发明人 WILLIAMS MICHAEL W.
分类号 G06F13/16;G11C11/406;(IPC1-7):G11C7/00 主分类号 G06F13/16
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