发明名称 |
Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer |
摘要 |
In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 mum or less, and a gate length of a memory cell is 0.2 mum or less.
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申请公布号 |
US6462373(B2) |
申请公布日期 |
2002.10.08 |
申请号 |
US20000725564 |
申请日期 |
2000.11.30 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIMIZU KAZUHIRO;SHIROTA RIICHIRO;KOIDO NAOKI;ARITOME SEIICHI;TSUNODA HIROAKI;IGUCHI TADASHI;NARITA KAZUHITO;TERASAKA KUNIHIRO;IIZUKA HIROHISA |
分类号 |
H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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