发明名称 |
METHOD FOR THE INTEGRATION OF RESISTORS AND ESD SELF-PROTECTED TRANSISTORS IN AN INTEGRATED DEVICE WITH A MEMORY MATRIX MANUFACTURED BY MEANS OF A PROCESS FEATURING SELF-ALIGNED SOURCE (SAS) FORMATION AND JUNCTION SALICIDATION |
摘要 |
A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a Self-Aligned Source masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region is formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type and exploiting the SAS masked implant used to form source regions of the matrix of memory cells. At least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.
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申请公布号 |
US6461922(B1) |
申请公布日期 |
2002.10.08 |
申请号 |
US19990464066 |
申请日期 |
1999.12.15 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
COLOMBO PAOLO;MAURELLI ALFONSO |
分类号 |
H01L21/336;H01L21/8247;H01L27/02;(IPC1-7):H01L21/331 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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