| 摘要 |
A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement. |
