Programmable timing boundary in dynamic circuits

摘要

A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.