| 摘要 |
A semiconductor integrated circuit is disclosed which includes a clock synchronous memory, an internal clock generating circuit, a clock selecting circuit, a data output converting circuit, and a data output selecting circuit. The clock synchronous memory is disposed to receive a control signal, an address signal, and a data input and provide an internal data output. The internal clock generating circuit is disposed to generate an internal clock signal having a frequency higher than that of an external clock signal. The clock selecting circuit is disposed to select between the external clock signal and the internal clock signal and send the selected clock signal to the clock synchronous memory. The data output converting circuit is disposed to convert the internal data output into an external data output in synchronization with a clock signal having a frequency lower than that of the internal clock signal. The data output selecting circuit is disposed to select between the internal data output and the external data output and provide the selected data output.
|
