发明名称 |
VIA FORMING METHOD IN MULTILAYER CIRCUIT BOARD |
摘要 |
PROBLEM TO BE SOLVED: To provide a via forming method which can contract the time required for a via forming process and can contribute to the increase of the density of wiring structures in a multilayer circuit board. SOLUTION: The via forming method in the multilayer circuit board includes a process for laminating a photoresist on its circuit wiring surface having a conductor layer; a process for so forming an opening portion in the photoresist by the exposure and development of the photoresist as to expose a portion of the conductor layer to the external; a process for so filling a conductive paste into the opening portion as to form a via post whose outer contour is specified by the opening portion; and a process for removing therefrom the photoresist. |
申请公布号 |
JP2002290048(A) |
申请公布日期 |
2002.10.04 |
申请号 |
JP20010086120 |
申请日期 |
2001.03.23 |
申请人 |
FUJITSU LTD |
发明人 |
TANI MOTOAKI;HAYASHI NOBUYUKI;MACHIDA HIROYUKI |
分类号 |
H05K3/40;H05K3/46;(IPC1-7):H05K3/46 |
主分类号 |
H05K3/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|