| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a fast Fourier transform circuit and a fast Fourier inverse transform circuit enabling to minimize an error caused by truncation of low order bits and to suppress the deterioration of precision in calculation even when the input level of input signal series is small. SOLUTION: The high speed Fourier transform circuit is provided with a loop for a butterfly calculation means constituted of a switch 101, a DPRAM 102, a first register 106, an adder 104, a subtracter 105, a second register 106, a third register 107, a phase coefficient generator 108, and a complex multiplier 109. The maximum value of input series of the butterfly calculation means is detected at a maximum detection part 301, a bit shifting of an output series of the butterfly calculation means is performed based on the bit width of maximum value and the high speed Fourier transform circuit at a shifter 302, and at the final round of the loop, the bit shift and the inverse bit shift are executed by the shifter 302.</p> |
