| 摘要 |
PROBLEM TO BE SOLVED: To make possible a fly-by transfer that transfers data directly between a synchronous memory (SDRAM) connected via an external general-purpose bus and an I/O memory for an external device. SOLUTION: In a direct memory access control system in accordance with the present invention, a ready signal READY1 indicating a read data effective state and a ready signals READY1 and 2 indicating a writable state are transferred between an input/output interface (180) and a memory interface (140). Until the later ready signal of whichever interface may be is generated, both interfaces retain the read data effective state and the writable state of the input/output memory and the synchronous memory which are under control of the interfaces. This configuration synchronizes the read data effective timing with the writable timing of the synchronous memory and the input/output memory, thus making it possible to transfer data between the two memories in a fly-by transfer mode. |
