| 摘要 |
A semiconductor memory device of which the data output circuit scale is reduced and the data read speed is improved. The output control signal generation portion 201 receives the first and second output data determination signals D and /D outputted from a sense amplifier, and a level shift enable signal EN_Vext. The first output data determination signal D and the second output data determination signal /D have a complementary relation with regard to their logical levels and their maximum voltage is an internal voltage Vint while their minimum voltage is a ground voltage GND. The maximum voltage of the level shift enable signal EN_Vext is the external voltage Vext and the minimum voltage is the ground voltage GND. An output portion 202 connected with the output control signal generation portion 201 through nodes n/P and n/N outputs an output signal DOUT from a node n232. The maximum voltage of the output signal DOUT is the external voltage Vext while the minimum voltage is the ground voltage GND.
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