发明名称 Method and apparatus for dynamic register management in a processor
摘要 A method for mapping a plurality of virtual registers to a plurality of physical registers is provided. Generally, a plurality of virtual registers are provided where each virtual register comprises physical register address bits. A status indicator for indicating the status of each virtual register is also provided. A processing device is also provided. The processing device has a plurality of physical registers. A plurality of virtual registers, wherein each virtual register comprises physical register address bits form part of the processing device. The processing device also has a status indicator for indicating a status of each virtual register.
申请公布号 US2002144091(A1) 申请公布日期 2002.10.03
申请号 US20010825753 申请日期 2001.04.03
申请人 WIDIGEN LARRY 发明人 WIDIGEN LARRY
分类号 G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/38
代理机构 代理人
主权项
地址