| 摘要 |
A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.
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