| 摘要 |
A multiplexer based adder circuit. The novel adder design is suitable for a number of bit sizes, but in one exemplary embodiment is a 64-bit adder. A complete 16-bit scaled adder is taught. The adder circuit is efficient and reconfigurable in that the adder can be partitioned to support a variety of data formats. The adder can add two 64-bit operands, four 32-bit operands, eight 16-bit operands, or sixteen 8-bit operands. The reconfigurability of the adder for different word sizes is achieved using only a small number of control signals for partitioning without increasing the adder size or reducing its speed. The novel adder circuit is designed using multiplexer circuits and two input inverted logic gates making the adder very fast. The adder design recognizes that pass transistor based multiplexer circuits and inverted logic gates are the fastest circuit elements for standard CMOS logic. In particular, the generate and propagate circuits of the carry tree each include a multiplexer and an inverted two input logic gate. The first level of the carry tree logic groups operand bits by groups of four thereby significantly reducing the logic required to generate the appropriate carry signals. The adder circuit is also optimized for hardware by having a hardware efficient circuit for performing selective addition. The adder can be used for multi-media applications and is also well suited for very long instruction word (VLIW) processors. The critical timing path of the adder includes 7 multiplexers and 1 XNOR gate, e.g., log(n)+1, where n is the number of bits of the adder.
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